Prof. Dr. phil. nat. Rolf Drechsler | Computer Science

Former PhD-Students

Rolf Drechsler
I attach great importance to supporting junior researchers. The following PhD theses were done in the Group of Computer Architecture, partly in collaboration with partners in science and industry. The list gives a chronical overview on our PhD students, along with the titles of their theses.


Dr. Pascal Pieper
Formal and Practical Techniques for the Complex System Design Process using Virtual Prototypes, 2023
Dr. Niklas Bruns
Virtual Prototype Centric Verification for Embedded System Development, 2023
Dr. Meywerk Tim
Modelling, Verification and Test of High-level Robotic Plans, 2023
Dr. Alireza Mahzoon
Formal Verification of Structurally Complex Multipliers, 2022
Dr. Buse Ustaoglu
Hardware Packages for Self-Verification and Secure Partial Reconfiguration, 2022
Dr. Saman Fröhlich
A Fully Fledged HDL Design Flow for In-Memory Computing with Approximation Support, 2022
Dr. Rehab Massoud
Evidence-Oriented Tracing and Verification | The Declaration of Timeprints, 2021
Dr. David Lemma
Specification Analysis for System-Level Power-Aware ASIC Design, 2021
Dr. Muhammad Hassan
Enhanced Modern Virtual Prototype based Verification Flow for Heterogeneous Systems, 2021
Dr. Fritjof Bornebusch
COQ meets CλaSH - Proposing a Hardware Design Synthesis Flow that Combines Proof Assistants with Functional Hardware Description Languages, 2021
Dr. Marcel Walter
Design Automation for Field-Coupled Nanotechnologies, 2021
Dr. Mazyar Seraj
Impacts of Block-based Programming on Young Learners' Programming Skills and Attitude in the Context of Smart Environments, 2020
Dr. Sebastian Huhn
Next Generation Design For Testability, Debug and Reliability Using Formal Techniques, 2020
Dr. Vladimir Herdt
Efficient Modeling, Verification and Analysis Techniques to Enhance the Virtual Prototype based Design Flow for Embedded Systems, 2020
Dr. Harshad Dhotre
Pattern Analysis for Power Safe Testing and Prediction Using Machine Learning, 2019
Dr. Mehran Goli
Automated Analysis of Virtual Prototypes at the Electronic System Level -Design Understanding and Applications-, 2019
Dr. Kenneth Schmitz
Trust is good, Control is better: A Container based System Design Scheme, 2019
Dr. Arighna Deb
Logic Synthesis Techniques for Optical Circuits, 2018
Assistant Professor at Kalinga Institute of Industrial Technology, India
Dr. Saeideh Shirinzadeh
Synthesis and Optimization for Logic-in-Memory Computing using Memristive Devices, 2018
Dr. Zaid Saleem Ali Al-Wardi
HDL-based Synthesis of Reversible Circuits | A Scalable Design Approach, 2018
Dr. Arun Chandrasekharan
Design Automation Techniques for Approximation Circuits, 2017
Dr. Oliver Keszöcze
Exact Design of Digital Microfluidic Biochips, 2017
Assistant Professor at Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany
Dr. Nils Przigoda
SMT-based Validation & Verification of UML/OCL Models, 2017
Dr. Amr Sayed-Ahmed
Highly Automated Formal Verification of Arithmetic Circuits, 2017
Dr. Jannis Stoppe
Non-Intrusive Analysis of Electronic System Level Designs in SystemC, 2017
Dr. Finn Haedicke
High-Quality Hardware Design and Verification using Word-Level Satisfiability Techniques, 2016
Dr. Ngouo'goum Tague Laura Sandrine
Using Decision Diagrams in the Design of Reversible Circuit, 2016
Dr. Eleonora Schönborn
Scalable Design and Synthesis of Reversible Circuits, 2016
Dr. Judith Peters
Exploiting MARTE/CCSL in Modern Design Flows, 2015
Dr. Nabila Abdessaied
Reversible and Quantum Circuits | Optimization and Complexity Analysis, 2015
Dr. Melanie Diepenbeck
Completing Behaviour Driven Development for Testing and Verification, 2015
Dr. Julia Seiter
Formal Model Refinement, 2015
Dr. Hoang M. Le
Automated Techniques for Functional Verification at the Electronic System Level, 2015
Dr. Shuo Yang
Improving Coverage in Simulation-based Verification, 2015
Dr. Marc Michael
Methoden zum Erfassen und Entwickeln von SystemC Modellen, 2014
Dr. Elsa Andrea Kirchner
Embedded Brain Reading, 2014
Professor at University of Duisburg-Essen (UDE), Germany
Dr. Mathias Soeken
Formal Specification Level Concepts, Methods, and Algorithms, 2013
Dr. Stefan Frehse
Quality and Quantity in Robustness Checking Using Formal Techniques, 2013
Dr. Hongyan Zhang
Testing of Reversible Circuits, 2013
Dr. Beate Kapturek
Vorgehensmodelle für die Technische Dokumentation Eingebetteter Systeme, 2013
Dr. Daniel Tille
Advanced Utilization of Formal Methods in Automatic Test Pattern Generation for Industrial Designs, 2011
Dr. Stephan Eggersglüß
Robust Algorithms for High Quality Test Pattern Generation Using Boolean Satisfiability, 2010
Dr. André Sülflow
WoLFram - A Word Level Framework for Formal Verification and its Application, 2010
Dr. Robert Wille
Towards a Design Flow for Reversible Logic, 2009
Professor at Technical University of Munich, Germany
Dr. Ulrich Kühne
Advanced Automation in Formal Verification of Processors, 2009
Associate Professor (Maître de Conférences) at Télécom ParisTech, France
Dr. Frank Rogin
An Integrated Approach to Utilize Designer's Debug Capacity in System-on-a-Chip Designs, 2009
Dr. Daniel Große
Quality-Driven Design and Verification Flow for Digital Systems, 2008
Professor at Johannes Kepler University Linz, Austria
Dr. Sebastian Kinder
Automated Validation and Verification of Railway Specific Components and Systems, 2008
Dr. Junhao Shi
Boolean Techniques in Testing of Digital Circuits, 2007
Dr. Görschwin Fey
Increasing Robustness and Usability of Circuit Design Tools by Using Formal Techniques, 2006
Professor at Hamburg University of Technology (TUHH), Germany
AGRA Genealogy

Mathematics Genealogy Project | Rolf Drechsler

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